1. Field of the Invention
Example embodiments of the present general inventive concept relate to methods of forming metal wires. More particularly, example embodiments of the present general inventive concept relate to methods of forming wire structures for electrical connection of active regions.
2. Description of the Related Art
Recently, a semiconductor device is developed fast as information media such as a computer is rapidly supplied. In an aspect of function, a semiconductor device is required to have a high operation speed and a large quantity of store capacity. A technology of manufacturing a semiconductor is developed to enhance integration degrees, a reliability and a response speed in order to satisfy the above requirements.
Semiconductor devices are divided into a random access memory (RAM) device and a read only memory (ROM) device. The RAM device such as a dynamic random access memory (DRAM) device or a static random access memory (SRAM) device is a volatile device, has a rapid input/output speed and loses data as time goes on. The ROM device may maintain data when the data is stored once, but have relatively slower input/output speed. Among the ROM devices, demands for an electrically erasable and programmable ROM (EEPROM) device electrically capable of inputting or outputting data or a flash memory device has increased. The flash memory device developing from the EEPROM controls input data or output data by F-N tunneling (Fowler-Nordheim tunneling) or a hot carrier injection.
Generally, a semiconductor device is manufactured by a fabrication (FAB) process forming electric circuits on a silicon wafer serving as a semiconductor substrate, an electrical die sorting (EDS) process examining electrical characteristics of the semiconductor devices formed in the FAB process and a package process encapsulating the semiconductor devices separately by an epoxy resin.
The FAB process includes a deposition process for forming layers on a semiconductor substrate, a chemical mechanical polishing (CMP) process for planarization the layers, a photolithography process for forming a photoresist pattern on the layers, an etching process for forming the layers into a pattern having electrical characteristics, an ion implantation process for implanting ions onto a portion of the semiconductor substrate, a washing process for removing impurities on the semiconductor substrate, an examining process for detecting defects of the semiconductor substrate having the layers and the pattern, and a process of forming wires on the semiconductor substrate.
The process of forming wires is generally performed using metal or metal nitride having electrical conductivity because a semiconductor is required to have high operation speed and a large quantity of store capacity. As large storage capacity and high operation speed are required, a chip has been reduced in size, and a method of forming a word line having a thin width is required. Accordingly, a method of forming a cell word line having a buried channel array transistor (BCAT) structure has been developed. However, when the wire is formed, a fence is formed at an active region, so that a reliability of the semiconductor device may be decreased.